[Back]

M. Mosbeck, D. Hauer, A. Jantsch:
"VELS: VHDL E-Learning System for Automatic Generation and Evaluation of Per-Student Randomized Assignments";
in: "2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)", issued by: IEEE; IEEE, Estland, Tallinn, 2018, ISBN: 978-1-5386-7656-1.

Learning digital design with VHDL requires extensive practice with solving many assignments independently, which is difficult to provide in a university setting with high student-teacher ratio. Automated assessment systems can help by facilitating a flexible, satisfying learning environment for students.
This paper describes the VHDL E-learning system VELS, its implementation, and our experience over the last three years with approximately 1000 students. VELS is a flexible system with key features including a uniform task system with parameterized tasks, non-static testbenches, communication over email, a tool that aids in creating new tasks, flexible configuration possibilities with different course modes, exchangeable simulator backend and multi language support.

VHDL, E-Learning, Automated Assessment

http://dx.doi.org/10.1109/NORCHIP.2018.8573455

https://publik.tuwien.ac.at/files/publik_276135.pdf