Contributions to Proceedings:

M. Schütz, A. Steininger, F. Huemer, J. Lechner:
"State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration";
in: "2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)", issued by: IEEE CS Press; IEEE Xplore Digital Library, 2018, ISBN: 978-1-5386-8398-9, 6 pages.

English abstract:
The operation of field-programmable gate arrays (FPGAs) in harsh environments like space entails the need for suitable fault-tolerance techniques of which Triple-Modular Redundancy (TMR) is most commonly deployed. While TMR is undoubtedly effective in masking faults, state recovery remains a problematic issue: Fine-grain TMR allows safe recovery, but incurs prohibitive area and performance penalties. In contrast, coarse-grain TMR has little overhead, but cannot safely provide recovery without roll-back or reset. We use the dynamic reconfiguration feature of modern FPGAs to augment an initially coarse-grain TMR with the ability of temporarily loading a fine-grain
TMR design for forward-state-recovery. Therefore, we can seamlessly resume correct (fully redundant) operation in case of data-as well as configuration faults that occurred in the FPGA. As a proof of concept, the paper presents a showcase design and discusses distinctive properties of this new approach.

FPGA, TMR, partial-reconfiguration, MTTF, state-recovery

"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)

Related Projects:
Project Head Andreas Steininger:
Intel CARS

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