Talks and Poster Presentations (with Proceedings-Entry):
M. Mosbeck, M. Meisel, M. Rathmair, A. Jantsch:
"VELS- VHDL E-Learning System for Automatic Generation and Evaluation of Per-Student Customized Tasks for Hardware Modeling Courses";
Poster: Microelectronic Systems Symposium (MESS18),
Wien;
04-12-2018
- 04-13-2018; in: "MESS18 Microelectronic Systems Symposium",
GMS - Gesellschaft für Mikroel (ed.);
OVE,
91
(2018),
ISBN: 978-3-903249-01-1;
34.
English abstract:
VHDL (Very High Speed Integrated Circuit Hardware Description Language) is a powerful hardware description language to design algorithms and functionalities to be automatically
converted to digital circuits. It is an important instrument for electrical engineering students. Unfortunately, decreasing teacher-to-student ratios limit the possibilities to offer personalized guidance based on students' needs. The goal of the VHDL E-Learning System (VELS) is to give students the possibilities to learn at their own pace and learn from their own mistakes while considering their previous knowledge.
Keywords:
VHDL, Asynchronous Learning, Distance Education, E-Learning
Electronic version of the publication:
https://publik.tuwien.ac.at/files/publik_277443.pdf
Created from the Publication Database of the Vienna University of Technology.