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J. Maier, M Függer, T. Nowak, U. Schmid:
"Transistor-Level Analysis of Dynamic Delay Models";
Talk: 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2019), Hirosaki, Japan; 2019-05-12 - 2019-05-15; in: "2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)", (2019), ISBN: 978-1-5386-4747-9; 76 - 85.

Delay estimation is a crucial task in digital circuit
design as it provides the possibility to assure the desired func-
tionality, but also prevents undesired behavior very early. For
this purpose elaborate delay models like the Degradation Delay
Model (DDM) and the Involution Delay Model (IDM) have been
proposed in the past, which facilitate accurate dynamic timing
analysis: Both use delay functions that determine the delay of
the current input transition based on the time difference T to
the previous output one. Currently, however, extensive analog
simulations are necessary to determine the (parameters of the)
delay function, which is a very time-consuming and cumbersome
task and thus limits the applicability of these models.
In this paper, we therefore thoroughly investigate the charac-
terization procedures of a CMOS inverter on the transistor level
in order to derive analytical expressions for the delay functions.
Based on reasonably simple transistor models we identify three
operation regions, each described by a different estimation
function. Using simulations with two independent technologies,
we show that our predictions are not only accurate but also
reasonably robust w.r.t. variations. Our results furthermore
indicate that the exponential fitting proposed for DDM is actually
only partially valid, while our analytic approach can be applied
on the whole range. Even the more complex IDM is predicted
reasonably accurate.

Circuit models, glitch propagation, delay mod- els, pulse degradation, model parameterization

http://dx.doi.org/10.1109/ASYNC.2019.00019