Talks and Poster Presentations (without Proceedings-Entry):

P. Paulweber, J. Maier, J. Cortadella:
"Unified (A)Synchronous Circuit Development";
Talk: 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2019), Hirosaki, Japan; 2019-05-12 - 2019-05-15.

English abstract:
Despite its development several decades ago and
several very beneficial properties asynchronous logic design,
which is data driven and runs as fast as possible in all situations,
is rarely used nowadays. Reasons are of course its disadvan-
tageous properties such as bad testability but also required
sophisticated knowledge for designers and missing tools. In this
paper we draw a path to tackle the latter points by suggesting
a tool/way to generate multiple circuit implementations from
a single description. We are aiming to convert specifications
written in various input languages, e.g. C or VHDL, to an unified
Internal Representation (IR). This IR is composed of building
blocks (semantic vocabulary) specified through the Abstract State
Machine (ASM) based formal method. The ASM artifact is then
used to generate the circuit in the desired (a)synchronous design
style. As short term goal we aim to train developers by reading
synchronous descriptions and converting them to asynchronous
designs however in the long run we hope to establish a unified
path for circuit development, which only requires an abstract
behavioral description.

Abstract State Machines, Asynchronous Logic

Created from the Publication Database of the Vienna University of Technology.