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D. Öhlinger, J. Maier, M Függer, U. Schmid:
"The Involution Tool for Accurate Digital Timing and Power Analysis";
Talk: 2019 IEEE 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2019), Rhodos; 2019-07-01 - 2019-07-03; in: "2019 IEEE 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2019)", (2019), ISBN: 978-1-7281-2103-1; 1 - 8.

We introduce the prototype of a digital timing sim-
ulation and power analysis tool for integrated circuit (Involution
Tool) which employs the involution delay model introduced by
̈
F ugger
et al. at DATE´15. Unlike the pure and inertial delay
models typically used in digital timing analysis tools, the involu-
tion model faithfully captures pulse propagation. The presented
tool is able to quantify for the first time the accuracy of the latter
by facilitating comparisons of its timing and power predictions
with both SPICE-generated results and results achieved by
standard timing analysis tools. It is easily customizable, both
w.r.t. different instances of the involution model and different
circuits, and supports automatic test case generation, including
parameter sweeping. We demonstrate its capabilities by providing
timing and power analysis results for three circuits in varying
technologies: an inverter tree, the clock tree of an open-source
processor, and a combinational circuit that involves multi-input
NAND gates. It turns out that the timing and power predictions
of two natural types of involution models are significantly better
than the predictions obtained by standard digital simulations
for the inverter tree and the clock tree. For the NAND circuit,
the performance is comparable but not significantly better. Our
simulations thus confirm the benefits of the involution model, but
also demonstrate shortcomings for multi-input gates.

Digital timing simulation, design tools, delay models, pulse degradation, glitch propagation.

http://dx.doi.org/10.1109/PATMOS.2019.8862165