Talks and Poster Presentations (with Proceedings-Entry):

A. Steininger, M. Schwendinger:
"A Systematic Approach to Clock Failure Detection";
Talk: Austrochip Workshop on Microelectronics, Wien; 2019-10-24; in: "2019 Austrochip Workshop on Microelectronics (Austrochip)", (2019), ISBN: 978-1-7281-1953-3; 35 - 42.

English abstract:
Many of today's chips comprise multiple clock domains and some even have multiple clock sources. This makes supervision of the correct operation of a clock increasingly important. Rather than promoting a specific approach for clock failure detection, this paper tries to provide a systematic overview of the available options. To this end, requirements and principles are identified and discussed first, and then related implementations are shown. These are partly revisiting existing solutions from the literature that are put into the context, and partly constituting novel solutions. The implementations are evaluated according to several criteria, like detection latency, implementation efforts, and, most notably, potential for metastability issues.
The purpose of the paper is to give the designer a guideline, showing which techniques are available, along with a critical assessment that shall help in making the appropriate choice for a given application.

clock monitoring; metastability; clock domain crossing; cycle counting; pure delay; elastic pipeline

"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)

Related Projects:
Project Head Andreas Steininger:
Intel CARS

Created from the Publication Database of the Vienna University of Technology.