[Back]

S. Ullah, H. Schmidl, S. Satyendra Sahoo, S. Rehman, A. Kumar:
"Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures";
IEEE Transactions on Computers, PP (2020), 1 - 8.

Multiplication is one of the most extensively used arithmetic operations in a wide range of applications. In order to provide resource-efficient and high-performance multipliers, previous works have proposed different designs of accurate and approximate multipliers-mainly for ASIC-based systems. However, the architectural differences between ASICs and FPGA-based systems limit the effectiveness of these multipliers for FPGA-based systems. Moreover, most of these multiplier designs are valid only for unsigned numbers. To bridge this gap, we propose a novel implementation technique for designing resource-efficient and low-power accurate and approximate signed multipliers which are optimized for FPGA-based systems. Compared to Vivado's area-optimized multiplier IPs, the designs obtained using our proposed technique occupy 47% to 63% less area (Lookup Tables). To accelerate further research in this direction and reproduce the presented results, the RTL and behavioral models of our proposed methodology are available as an open-source library at https:// cfaed.tu-dresden.de/pd-downloads.

Field programmable gate arrays, Performance gain , Table lookup , Signal processing algorithms, Libraries,Digital signal processing, Delays

http://dx.doi.org/10.1109/TC.2020.2988404