Vorträge und Posterpräsentationen (mit Tagungsband-Eintrag):
M. Platzer, P. Puschner:
"A Processor Extension for Time-Predictable Code Execution";
Vortrag: 2021 IEEE 24th International Symposium on Real-Time Distributed Computing (ISORC),
Daegu, South Korea;
01.06.2021
- 03.06.2021; in: "2021 IEEE 24th International Symposium on Real-Time Distributed Computing (ISORC)",
C. Ceballos (Hrg.);
IEEE,
IEEE
(2021),
ISSN: 2375-5261;
S. 34
- 42.
Kurzfassung englisch:
In this paper, we present an instruction filter, a simple architecture extension that adds support for fully predicated execution to existing processor cores that do not natively support it. This makes single-path code execution and hence high quality and easily derivable worst-case execution time (WCET) information available for a wide range of processors. We have implemented the single-path instruction filter for two processors and evaluated it on the TACLe benchmark collection. The results demonstrate that despite the seeming inefficiency of single-path code, our method does not substantially increase the WCET. Therefore, running single-path code on processors with our instruction filter represents a competitive method for time-predictable code execution.
Schlagworte:
real-time systems, single-path code, predictable timing
"Offizielle" elektronische Version der Publikation (entsprechend ihrem Digital Object Identifier - DOI)
http://dx.doi.org/10.1109/ISORC52013.2021.00016
Elektronische Version der Publikation:
https://publik.tuwien.ac.at/files/publik_296582.pdf
Erstellt aus der Publikationsdatenbank der Technischen Universität Wien.