Talks and Poster Presentations (with Proceedings-Entry):

M. Platzer, P. Puschner:
"A Processor Extension for Time-Predictable Code Execution";
Talk: 2021 IEEE 24th International Symposium on Real-Time Distributed Computing (ISORC), Daegu, South Korea; 2021-06-01 - 2021-06-03; in: "2021 IEEE 24th International Symposium on Real-Time Distributed Computing (ISORC)", C. Ceballos (ed.); IEEE, IEEE (2021), ISSN: 2375-5261; 34 - 42.

English abstract:
In this paper, we present an instruction filter, a simple architecture extension that adds support for fully predicated execution to existing processor cores that do not natively support it. This makes single-path code execution and hence high quality and easily derivable worst-case execution time (WCET) information available for a wide range of processors. We have implemented the single-path instruction filter for two processors and evaluated it on the TACLe benchmark collection. The results demonstrate that despite the seeming inefficiency of single-path code, our method does not substantially increase the WCET. Therefore, running single-path code on processors with our instruction filter represents a competitive method for time-predictable code execution.

real-time systems, single-path code, predictable timing

"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)

Electronic version of the publication:

Created from the Publication Database of the Vienna University of Technology.