Talks and Poster Presentations (with Proceedings-Entry):
M. Platzer, P. Puschner:
"Vicuna: A Timing-Predictable RISC-V Vector Coprocessor for Scalable Parallel Computation";
Talk: 33rd Euromicro Conference on Real-Time Systems (ECRTS 2021),
- 2021-07-09; in: "33rd Euromicro Conference on Real-Time Systems (ECRTS 2021)",
B. Brandenburg (ed.);
Schloss Dagstuhl - Leibniz-Zentrum für Informatik,
In this work, we present Vicuna, a timing-predictable vector coprocessor. A vector processor can be scaled to satisfy the performance requirements of massively parallel computation tasks, yet its timing behavior can remain simple enough to be efficiently analyzable. Therefore, vector processors are promising for highly parallel real-time applications, such as advanced driver assistance systems and autonomous vehicles. Vicuna has been specifically tailored to address the needs of real-time applications. It features predictable and repeatable timing behavior and is free of timing anomalies, thus enabling effective and tight worst-case execution time (WCET) analysis while retaining the performance and efficiency commonly seen in other vector processors. We demonstrate our architecture´s predictability, scalability, and performance by running a set of benchmark applications on several configurations of Vicuna synthesized on a Xilinx 7 Series FPGA with a peak performance of over 10 billion 8-bit operations per second, which is in line with existing non-predictable soft vector-processing architectures.
Real-time Systems, Vector Processors, RISC-V
"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
Electronic version of the publication:
Created from the Publication Database of the Vienna University of Technology.