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Y. Elderhalli, N. El-Araby, O. Hasan, A. Jantsch, S. Tahar:
"Dynamic Fault Tree Models for FPGA Fault Tolerance and Reliability";
Vortrag: IEEE Annual Symposium on VLSI (ISVLSI), Montpellier; 07.07.2021 - 09.07.2021; in: "2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)", (2021), ISSN: 2159-3477; S. 194 - 199.

Field Programmable Gate Arrays (FPGAs) are widely used in many safety-critical applications mainly due to their high computational efficiency and dynamic reconfiguration. Although dynamic reconfigurability is often leveraged upon to attain further flexibility and reliability, it comes with an area overhead. In this paper, we provide a methodology to analyze the trade-off between reliability and area in dynamically reconfigured FPGA systems. We mainly aim to find the lowest area overhead for a given fault recovery rate in different system modules. For this purpose, we provide a generic model for system reliability using Dynamic Fault Trees (DFTs) that considers partially reconfigurable fallback units. The experiments are performed on a fail safe Electronic Control Units (ECUs) based automotive system. We use the FPGA partial reconfiguration to replace the faulty ECU functionality. The results show that by setting a suitable threshold for the reliability enhancement, the minimum number of fallback units can be determined. This leads to an enhanced system reliability with the most optimal area overhead.

FPGA, Reliability, Fault Tree Models

http://dx.doi.org/10.1109/ISVLSI51109.2021.00044