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B. Tutzer, C. Krieg, C. Wolf, A. Jantsch:
"Python Wraps Yosys for Rapid Open-Source EDA Application Development";
Vortrag: First Workshop on Open-Source Design Automation (OSDA) 2019, Florenz; 29.03.2019; in: "Proceedings of the First Workshop on Open-Source Design Automation (OSDA) 2019", (2019), 4 S.

Yosys is an open-source synthesis and verification
tool which natively supports Verilog-2005 and offers a variety
of passes to allow a user to adapt the design and verification
flow. A user can extend the functionality of Yosys with a plugin
interface in C++. C++ is a powerful language, and it is easy
to lose track in fixing low-level issues like memory allocation,
instead of focusing on the original problem. This can significantly
increase the length of the compile/debug cycle. Python, on the
other hand, is a dynamically-typed, garbage-collected language
which takes away low-level management from the user, who can
focus on the original problem, and therefore keep the debug cycle
short. Python is simple and easy to learn. We therefore propose
pyosys, a script that generates Boost.Python wrappers around the
C++ implementation of Yosys. These wrappers maintain seamless
interoperability between C++ and Python. pyosys makes Python´s
success accessible to Yosys: rapid application development. With
pyosys, a user can interactively use Yosys in a Python session,
with direct access to the Yosys data structures (e.g., design,
modules, cells, wires) and methods (e.g., run pass, load plugin,
get selection). In addition, the user can develop passes step-
by-step directly in Python, with immediate feedback and debug
capabilities. This is significant for scientists who can now test
their algorithms using an easy-to-use and maintainable high-
level language. The results of their experiments are stored
in Python objects, and can be directly processed with data
analysis frameworks like scipy, machine learning libraries such
as TensorFlow, and data visualization frameworks like matplotlib.

Yosys is an open-source synthesis and verification
tool which natively supports Verilog-2005 and offers a variety
of passes to allow a user to adapt the design and verification
flow. A user can extend the functionality of Yosys with a plugin
interface in C++. C++ is a powerful language, and it is easy
to lose track in fixing low-level issues like memory allocation,
instead of focusing on the original problem. This can significantly
increase the length of the compile/debug cycle. Python, on the
other hand, is a dynamically-typed, garbage-collected language
which takes away low-level management from the user, who can
focus on the original problem, and therefore keep the debug cycle
short. Python is simple and easy to learn. We therefore propose
pyosys, a script that generates Boost.Python wrappers around the
C++ implementation of Yosys. These wrappers maintain seamless
interoperability between C++ and Python. pyosys makes Python´s
success accessible to Yosys: rapid application development. With
pyosys, a user can interactively use Yosys in a Python session,
with direct access to the Yosys data structures (e.g., design,
modules, cells, wires) and methods (e.g., run pass, load plugin,
get selection). In addition, the user can develop passes step-
by-step directly in Python, with immediate feedback and debug
capabilities. This is significant for scientists who can now test
their algorithms using an easy-to-use and maintainable high-
level language. The results of their experiments are stored
in Python objects, and can be directly processed with data
analysis frameworks like scipy, machine learning libraries such
as TensorFlow, and data visualization frameworks like matplotlib.

Electronic design automation, Yosys, hardware synthesis

https://publik.tuwien.ac.at/files/publik_285808.pdf